In a static RAM, data is written to and read from a cell among a plurality of cells determined by an address. In a burn-in test for such a memory, i.e., in a test of applying stresses of "0" and "1" to all flip-flop cells at a high temperature, addresses are sequentially changed to select one cell after another to apply an electric field stress corresponding to data "0" and "1". In recent memory systems, in order to reduce power consumption, a power-down function is used, namely a closing a word line after a predetermined time lapse after each cell is selected. Therefore, even if a cell is selected by an address, the time period while the word line is actually opened is very short. This can be understood from a simple timing chart of selecting a cell, as shown in FIG. 18. Specifically, when an address transits (A), this transition is detected by an address transition detector (ATD) (B). A timer then starts operating (C) to activate a selected word line (D). Thereafter, the timer stops (C) to inactivate the selected word line. It takes a long time to apply stresses to all cells for a certain time period.
This problem will be further described in detail below. In a semiconductor memory (static RAM) having a timer circuit, a memory cell is activated for a time period predetermined by the timer circuit, for the data read/write. During the data read/write, each memory cell is activated only for the predetermined time period. Therefore, sufficient stress is not applied to a memory cell during a stress applying test (burn-in test or the like), as compared to the stress application to a memory cell without using such a timer circuit. For this reason, it becomes important to select an optimum test method in order to remove defective memory cells.
FIG. 19 shows a simplified system arrangement of a semiconductor memory (static RAM). This system operates in the following manner in order to reduce current consumption. Namely, data in a memory cell of a memory cell array MCA is stored via a sense amplifier SA in an output data latch circuit DLC. Thereafter, the decoder and sense amplifier SA are inactivated by using a timer circuit TC. The timer circuit TC determines the time period during which a memory cell is activated. The shorter the time period while the timer circuit TC activates the memory system, the more the power consumption reduces. However, the total stress test time becomes very long in order to apply sufficient stresses and reliably remove defective memory cells. It becomes therefore necessary to provide some alternative test method.
FIG. 20 Shows the operation during a read cycle of the static RAM shown in FIG. 19. Nodes a to f in FIG. 19 correspond to (A) to (F) shown in FIG. 20.
When an address (a) is fixed, a pulse (b) rises. When the pulse (b) rises, a decoder (d) and a timer (c) start operating. Data in a memory cell selected by an output from the decoder (d) is latched by an output data latch circuit (e), and the latched data is outputted (f). Thereafter, the timer (c) causes operations of the decoder and sense amplifier to stop.
As seen from FIG. 20, a memory cell inactive period T1 extends in time fixing from the address (a) to the time when the decoder (d) delivers an output, a memory cell active period T2 is from when the decoder (d) delivers an output to when the decoder (d) stops delivering its output, and another memory cell inactive period T3 is from when the decoder (d) stops delivering its output to when the next address (a) is fixed.
It is also possible during a write cycle to activate a memory cell for a predetermined time period by using the timer circuit TC. The operations of the timer circuit TC and decoder (d) are the same as during the read cycle.
FIG. 21 shows an example of a conventional timer circuit TC. The timer circuit TC receives .phi..sub.ATD (address transition detector output), .phi..sub.WE (WE output signal), .phi..sub.DTD (data transition detector output), and other signals, and sets a desired delay time using a delay circuit DLY.
A NOR-ed signal of the input signals to the timer circuit TC is delayed by the delay circuit DLY having inverters and NAND gates, to obtain an output .phi..sub.p for the control of the word line and sense amplifier.
The above-described problem of a long test time also becomes significant as the capacity of a memory increases. Namely, in a stress application test for memory cells of a semiconductor memory, cells are sequentially selected to apply stresses thereto. Therefore, it takes a very long time to apply sufficient stresses to all cells, as the capacity of the memory increases.
More specifically, data is read from and written into a memory cell among a plurality of memory cells of a semiconductor memory (static RAM) determined by inputted address signals. As the capacity of a memory increases and so the number of memory cells increases, there arises a problem of a very long time in applying sufficient stresses to all cells and removing defective cells during a stress application test.
As described above, a conventional semiconductor memory has the following disadvantages.
Namely, it takes a considerably long time to apply stresses to all memory cells during a burn-in test or the like, because stress is applied sequentially to one memory cell after another.
Furthermore, for a semiconductor memory having a power-down function with a memory cell active period being determined by a timer circuit, it is difficult to apply sufficient stress to each memory cell, because the memory cell active period is limited to a short time period.